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enpirion ? power datasheet ep5358 x ui 600ma powersoc synchronous buck regulator with integrated inductor description the ep5358 xui (x = l or h) is rated for up to 6 00ma of continuous output current. the ep5358 xui integrates mosfet switches, control, compensation, and the magnetics in an advanced 2.5mm x 2.25mm micro - qfn package. integrated magnetics enables a tiny solution footprint, low output ripple, low part - count, and high reliability, while maintaining hi gh efficiency. the complete solution can be implemented in as little as 1 4 mm 2 . the ep5358 xui uses a 3 - pin vid to easily select the output voltage setting. output voltage settings are available in 2 optimized ranges providing coverage for typical v out set tings. the vid pins can be changed on the fly for fast dynamic voltage scaling. ep5358 lui further has the option to use an external voltage divider. the ep5358xui is a perfect solution for noise sensitive and space constrained applications that require high efficiency. ep 5358 xui 2.2uf 10uf 4. 75 mm 2.25mm figure 1: total s olution footprint. features ? integrated inductor technology ? 2.5mm x 2.25mm x 1.1mm uqfn package ? total solution footprint 1 4 mm 2 ? low v out ripple for rf compatibility ? high efficiency, up to 93% ? up to 6 00ma continuous output current ? less than 1 a standby cur rent ? 5 mhz switching frequency ? 3 pin vid for glitch free voltage scaling ? v out range 0.6v to v in ? 0.25v ? short circuit and over current pr otection ? uvlo and thermal protection ? ic level reliability in a powersoc solution application ? wireless and rf applications ? wireless broad band data cards ? small form factor optical modules ? low noise fpga io and transceivers ? advanced low power processors, ds p, io, memory, video, multimedia engines figure 2: typical application schematic v out 2.2uf pgnd ep5358hui enable pv in v s0 v s1 v s2 v sense v out 10uf agnd av in v in www.altera.com/enpirion 03541 october 11, 2013 rev f
e p5358lui/ep5358hui ordering information part number comment package ep5358 lui low vid range 16- pin qfn t&r ep5358hui high vid range 16 - pin qfn t&r evb-ep5358lui e p5358 lui evaluation board EVB-EP5358HUI e p5358 hui evaluation board pin assignments (top view) figure 3: ep5358 lui pin out diagram (top view) figure 4 : ep5358 hui pin out diagram (top view) pin description pin n am e function 1 , 15, 16 nc(sw) no connect ? these pins are internally connected to the common switching node of the internal mosfets. nc (sw) pins are not to be electrically connected to any external signal, ground, or voltage. however, they must be soldered to the pcb. failure to follow this guideline may result in part malfunction or damage to the device. 2 ,3 pgnd power ground. connect t hese pins tog ether and to the ground electrode of the input and output filter capacitors. 4 vfb/nc ep5358 lui: feed back pin for external divider option. ep5358 hui: no connect 5 vsense sense pin for preset output voltages. refer to application section for proper configuration . 6 agnd analog ground. this is the quiet ground for the internal control circuitry, and the ground return for external feedback voltage divider 7, 8 vout regulated output voltage. refer to application section for proper layout and decoup ling. 9, 10, 11 vs2, vs1, vs0 output voltage select. vs2 = pin 9, vs1 = pin 10 , vs0 = pin 11. ep5358 lui: selects one of seven preset output voltages or an external resistor divider. ep5358 hui: s elects one of eight preset output voltages. (refer to section on output voltage select for more details.) 12 enable output enable. enable = logic high; disable = logic low 13 avin input power supply for the controller circuitry. 14 pvin input voltage for the mosfet switches. pvin avin enable vs0 vs1 vs2 nc(sw) pgnd pgnd vfb vsense agnd vout vout nc(sw) nc(sw) ep5358lui 3 1 4 2 6 5 16 15 7 8 12 11 13 10 9 14 pvin avin enable vs0 vs1 vs2 nc(sw) pgnd pgnd nc vsense agnd vout vout nc(sw) nc(sw) ep5358hui 3 1 4 2 6 5 16 15 7 8 12 11 13 10 9 14 www.altera.com/enpirion page 2 03541 october 11, 2013 rev f
ep5358lui/ep5358hui absolute maximum ratings caution: absolute maximum ratings are stress ratings only. functional operation beyond the recommended operating conditions is not implied. stress beyond the absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability . parameter symbol min m ax units input supply voltage v in - 0. 3 6.0 v voltages on: enable , v sense , v so ? v s2 - 0.3 v in + 0.3 v voltages on: v fb ( ep5358 lui) - 0. 3 2. 7 v maximum operating junction temperature t j- abs 150 c storage temperature range t stg - 65 150 c reflow temp, 10 sec, msl3 jedec j - std - 020 c 260 c esd rating (based on h uman b ody m ode ) 2000 v recommended operating conditions parameter symbol min m ax units input voltage range v in 2. 4 5.5 v operating ambient temperature t a - 40 +8 5 c operating junction temperature t j - 40 + 125 c thermal characteristics parameter symbol typ units thermal resistance: junction to ambient ? 0 lfm ( note 1 ) ja 85 c/w thermal overload trip point t j- tp +155 c thermal overload trip point hysteresis 25 c note 1 : based on a four layer copper board and proper thermal design per jedec eij/jesd51 s tandards www.altera.com/enpirion page 3 03541 october 11, 2013 rev f
ep5358lui/ep5358hui electrical characteristics note: t a = - 40c to +85 c unless otherwise noted. typical values are at t a = 25c, vin = 3.6v . c in = 4.7 f mlcc , c out = 10 f parameter symbol test conditions min typ m ax units operating input voltage range v in 2. 4 5.5 v under voltage lock - out ? v in rising v uvlo _r 2. 0 v under voltage lock - out ? v in falling v uvlo _f 1.9 v drop out resistance r do input to output resistance in 100% duty cycle operation. 350 500 m ? output voltage range v out ep5358 lui (v do = i load x r do ) ep5358 hui 0.6 1.8 v in -v do 3.3 v dynamic voltage slew rate (vid change) v slew ep5358 lui ep5358 hui 4 8 v/ms vid preset v out initial accuracy ' v out t a = 25 q c , v in = 3.6v; i load = 100ma ; 0.8v v out 3.3 v -2 +2 % line regulation ' v out_l ine 2.4v v i v out_temp l - 40q c t a + 85q c 24 ppm / q c output current i out 6 00 ma shut - down current i sd enable = low 0.75 a ocp threshold i lim 2.4v v v out 3.3 v 1.25 1.4 a feedback pin voltage initial accuracy v fb t a = 25 q c , v in = 3.6v; i load = 100ma ; 0.8v v out 3.3v .588 0.6 0.612 v feedback pin input current i fb note 1 <100 na vs0 - vs2, pin logic low v vslo 0.0 0.3 v vs0 - vs2, pin logic high v vshi 1.4 v in v vs0 - vs2, pin input current i vsx note 1 <100 na enable pin logic low v enlo 0.3 v enable pin logic high v enhi 1.4 v enable pin current i enable note 1 <100 na operating frequency f osc 5 mhz soft start operation soft start slew rate ' v ss ep5358 l ui (vid mode) ep5358 h ui (vid mode) 2.6 5.2 4 8 5.4 10.8 v/ms v out rise time t rise ep535 8lui vfb mode 146 225 304 usec note 1 : parameter guaranteed by design www.altera.com/enpirion page 4 03541 october 11, 2013 rev f
ep5358lui/ep5358hui typical performance characteristics efficiency vs. load current: v in = 5.0 v, v out (f rom top to bottom) = 3.3 , 2.5 , 1.8 , 1.2 v efficiency vs. load current: v in = 3.7 v, v out (f rom top to bottom) = 2.5 , 1.8 , 1.2 v efficiency vs. load current: v in = 3.3 v, v out (f rom top to bottom) = 2.5 , 1.8 , 1.2 v start up waveform: v in = 5.0v , v out = 3.3 v; i load = 10ma (vid mode) start up waveform: v in = 5.0v , v out = 3.3 v; i l oad = 5 00ma (vid mode) 45 50 55 60 65 70 75 80 85 90 95 0 200 400 600 load current (ma) efficiency (%) 45 50 55 60 65 70 75 80 85 90 95 0 200 400 600 load current (ma) efficiency (%) 45 50 55 60 65 70 75 80 85 90 95 0 200 400 600 load current (ma) efficiency (%) www.altera.com/enpirion page 5 03541 october 11, 2013 rev f
ep5358lui/ep5358hui shut - down waveform: v in = 5.0v , v out = 3.3 v; i load = 10ma shut - down waveform: v in = 5.0v , v out = 3.3 v; i load = 500ma output ripple: v in = 5.0 v, v out = 1.2v , load = 500ma output ripple: v in = 5.0 v, v out = 3.3 v load = 500ma output ripple: v in = 3.3 v, v out = 1. 8v load = 500ma output ripple: v in = 3.3 v, v out = 1.2v , load = 500ma www.altera.com/enpirion page 6 03541 october 11, 2013 rev f
ep5358lui/ep5358hui load transient: v in = 5.0v, v out = 1.2v load stepped from 10ma to 500ma load transient: v in = 3.3 v, v out = 1. 8v load stepped from 10ma to 500ma www.altera.com/enpirion page 7 03541 october 11, 2013 rev f
ep5358lui/ep5358hui functional block diagram figure 5: functional block diagram pv in enable nc(sw) v sense vs0 vs1 vs2 av in agnd voltage select dac switch vref (+) (-) error amp v fb v out package boundry p-drive n-drive uvlo thermal limit current limit soft start sawtooth generator (+) (-) pwm comp gnd logic compensation network ep5358ui www.altera.com/enpirion page 8 03541 october 11, 2013 rev f
ep5358lui/ep5358hui detailed description functional overview the ep5358 xui requires only 2 small mlcc capacitors for a complete dc - dc converter solution. the device integrates mosfet switches, pwm controller, gate - drive, compensation, and inductor into a tiny 2.5 mm x 2.25 mm x 1.1mm micro - qfn package. advanced package design, along with the high level of integration, provides very low output ripple and noise. the ep5358 xui uses voltage mode control for high noise immunity and load matching to advanced 90nm loads. a 3 - pin vid allows the user to choose from one of 8 output vo ltage settings. the ep5358 xui comes with two vid output voltage ranges. the ep5358 hui provides v out settings from 1.8v to 3.3v, the ep5358 lui provides vid settings from 0.8v to 1.5v, and also has an external resistor divider option to program output setting over the 0.6v to v in - 0.25v range. the ep5358 xui provides the industry?s highest power density of any 6 00ma dcdc converter solution. the key enabler of this revolutionary integration is altera ?s proprietary power mosfet technology. the advanced mosfet switches are implemented in deep - submicron cmos to supply very low switching loss at high switching frequencies and to allow a high level of integration. the semiconductor process allows seem - less integration of all switching, control, and compensation ci rcuitry. the proprietary magnetics design provides high - density/high- value magnetics in a very small footprint. altera enpirion magnetics are carefully matched to the control and compensation circuitry yielding an optimal solution with assured performance over the entire operating range. protection features include under - voltage lock - out (uvlo), over - current protection (ocp), short circuit protection, and thermal overload protection. integrated inductor: low - noise low - emi the ep5358 xui utilizes a proprie tary low loss integrated inductor. the integration of the inductor greatly simplifies the power supply design process. the inherent shielding and compact construction of the integrated inductor reduces the conducted and radiated noise that can couple into the traces of the printed circuit board. further, the package layout is optimized to reduce the electrical path length for the high di/dt input ac ripple currents that are a major source of radiated emissions from dc- dc converters. the integrated induct or provides the optimal solution to the complexity, output ripple, and noise that plague low power dcdc converter design. control matched to sub 90nm loads the ep5358 xui utilizes an integrated type iii compensation network. voltage mode control is inheren tly impedance matched to the sub 90nm process technology that is used in today?s advanced ics. voltage mode control also provides a high degree of noise immunity at light load currents so that low ripple and high accuracy are maintained over the entire lo ad range. the very high switching frequency allows for a very wide control loop bandwidth and hence excellent transient performance. soft start internal soft start circuits limit in - rush current when the device starts up from a power down condition or whe n the ?enable? pin is asserted ?high?. digital control circuitry limits the v out ramp rate to levels that are safe for the power mosfets and the integrated inductor. the ep5358 hui has a soft - start slew rate that is twice that of the ep5358 lui. when the ep53 58 lui is configured in external resistor divider mode, the device has a fixed vout ramp time. therefore, the ramp rate will vary with the output voltage setting. output voltage ramp time is given in the electrical characteristics table. www.altera.com/enpirion page 9 03541 october 11, 2013 rev f
ep5358lui/ep5358hui excess bulk capacitance on the output of the device can cause an over - current condition at startup. the maximum total capacitance on the output, including the output filter capacitor and bulk and decoupling capacitance, at the load, is given as: ep5358 lui: c out_total_max = c out _fi lter + c out _bulk = 2 3 0uf ep5358 hui: c out_total_max = c out _fi lter + c out _bulk = 1 15uf ep53 58 lui in external divider mode: c out_total_max = 2.086 x10 -4 /v out farads the above numbers and formula assume a no load condition. over current/short circuit protection the current limit function is achieved by sensing the current flowing through a sense p - mosfet which is compared to a reference current. when this level is exceeded the p - fet is turned off and the n - fet is turned on, pulli ng v out low. this condition is maintained for approximately 0.5ms and then a normal soft start is initiated. if the over current condition still persists, this cycle will repeat. under voltage lockout during initial power up an under voltage lockout ci rcuit will hold - off the switching circuitry until the input voltage reaches a sufficient level to insure proper operation. if the voltage drops below the uvlo threshold the lockout circuitry will again disable the switching. hysteresis is included to pr event chattering between states. enable the enable pin provides a means to shut down the converter or enable normal operation. a logic low will disable the converter and cause it to shut down. a logic high will enable the converter into normal operation . not e: the enable pin must not be left floating. thermal shutdown when excessive power is dissipated in the chip, the junction temperature rises. once the junction temperature exceeds the thermal shutdown temperature the thermal shutdown circuit turns off the converter output voltage thus allowing the device to cool. when the junction temperature decreases by 15c , the device will go through the normal startup process. www.altera.com/enpirion page 10 03541 october 11, 2013 rev f
ep5358lui/ep5358hui application information v in vsense pvin v s1 v s2 v s0 10 f 4.7 f v out vout agnd enable pgnd avin figure 6: application circuit, ep5358 hui,. v in vsense pvin v s1 v s2 v s0 10 f 4.7 f v out vout agnd enable vfb pgnd avin figure 7 : application circuit, ep5358 l ui, showing the v fb function. output voltage programming the ep5358 xui utilizes a 3 - pin vid to program the output voltage value. the vid is available in two sets of output vid programming ranges. the vid pins should be connected either to avin or to agnd to avoid noise coupling into the device. the ?low? range is optimized for low voltage applications. it comes with preset vid settings ranging from 0.80v and 1.5v. this vid set also has an external divider option. to specify this vid range, order part number ep5358 lui. the ?high? vid set provides output voltage sett ings ranging from 1.8v to 3.3v. this version does not have an external divider option. to specify this vid range, order part number ep5358 hui. internally, the output of the vid multiplexer sets the value for the voltage reference dac, which in turn is co nnected to the non - inverting input of the error amplifier. this allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected. note: the vid pins must not be left floating. ep5358 l low vid range programming the ep5358 lui is designed to provide a high degree of flexibility in powering applications that require low v out settings and dynamic voltage scaling (dvs). the device employs a 3- pin vid architecture that allows the user to ch oose one of seven (7) preset output voltage settings, or the user can select an external voltage divider option. the vid pin settings can be changed on the fly to implement glitch - free voltage scaling. table 1 : ep5358 lui vid volt age select settings table 1 shows the vs2 - vs0 pin logic states for the ep5358 lui and the associated output voltage levels. a logic ?1? indicates a connection to avin or to a ?high? logic voltage level. a logic ?0? indicates a connection to agnd or to a ?low? logic voltage level. these pins can be either hardwired to avin or agnd or alternatively can be driven by standard logic levels. logic levels are defined in t he electrical characteristics table. any level between the logic high and logic low is indeterminate. ep5358 lui external voltage divider the external divider option is chosen by connecting vid pins vs2 - vs0 to v in or a logic ?1? or ?high?. the ep5358lu i uses a separate feedback pin, v fb , when using the external divider. v sense must be connected to v out as indicated in figure 8 . vs2 vs1 vs0 vout 0 0 0 1.50 0 0 1 1.45 0 1 0 1.20 0 1 1 1.15 1 0 0 1.10 1 0 1 1.05 1 1 0 0.8 1 1 1 ext www.altera.com/enpirion page 11 03541 october 11, 2013 rev f
ep5358lui/ep5358hui v in vsense vso vs2 ep5358lui 10 f 4.7 uf v out vout agnd enable ra rb vfb vs 1 pgnd avin pvin figure 8 : ep5358 lui using external divider the output voltage is selected by the following formula: ( ) rb ra out vv += 16.0 r a must be chosen as 237k ? to maintain loop gain. then r b is given as: ? ? = 6.0 102.142 3 out b v x r v out can be programmed over the range of 0.6v to (v in ? 0.25v). note: dynamic voltage scaling is not allowed between internal preset voltages and external divider. ep5358 hui high vid range programming the ep5358 hui v out settings are optimized for higher nominal voltages such as those required to power io, rf, or ic memory. the preset voltages range from 1.8v to 3.3v. there are eight (8) preset output voltage settings. the ep5358 hui does not have an external divider option. as with the ep5358 lui, the vid pin settings can be changed while the device is enabled. table 2 shows the vs0 - vs2 pin logic states for the ep5358 hui and the associated output voltage levels. a logic ?1? indicates a connection to avin or to a ?high? logic voltage l evel. a logic ?0? indicates a connection to agnd or to a ?low? logic voltage level. these pins can be either hardwired to avin or agnd or alternatively can be driven by standard logic levels. logic levels are defined in the electrical characteristics ta ble. any level between the logic high and logic low is indeterminate. these pins must not be left floating. table 2 : ep5358 h ui vid voltage select settings custom vid setting adjustment avin pvin enable vsense vout agnd pgnd 5.0 pf rs 10uf 4.7 uf ep 5358 xui vs2 vs1 vso figure 9 : ep5358 x ui with rc inserted in vsense path to modify vid output voltages. it is possible to adjust vout for a given vid setting by inserting a parallel rc combination in the vsense path as shown in figure 9 . the capacitor value is 5.0pf to ensure stability. note that the value of vout can only be increased from its nominal setting (vout new >vout old ): for ep5358lui: kohms vout vout rs old new l ? ? ? ? ? ? ? = 1 *711 for ep5358hui: kohms vout vout rs old new h ? ? ? ? ? ? ? = 1 *356 vout new is the desired ?new? vout. vs2 vs1 vs0 vout 0 0 0 3.3 0 0 1 3.0 0 1 0 2.9 0 1 1 2.6 1 0 0 2.5 1 0 1 2.2 1 1 0 2.1 1 1 1 1.8 www.altera.com/enpirion page 12 03541 october 11, 2013 rev f
ep5358lui/ep5358hui vout old is the vid table output voltage. for a given rs value, the vout new for vid settings is determined by the following equations: ep5358lui: volts rs vout vout l old new ? ? ? ? ? ? + ? ? ? ? ? ? = 1 711 ep5358hui: volts rs vout vout h old new ? ? ? ? ? ? + ? ? ? ? ? ? = 1 356 note: the amount of adjustment is limited to approximately 15% of the nominal vid setting. note: adjusting vout using this method will increase the tolerance of the output voltage. the larger the adjustment, the greater the increase in tolerance. power - up /down sequencing during power - up, enable should not be asserted before pvin, and pvin should not be asserted before avin. the pvin should never be powered when avin is off. during power down, the avin should not be powered down before the pvin. tying pvin and avin or all three pins (avin, pvin, enable) toget her during power up or power down meets these requirements . pre - bias start - up the ep5 3 58xu i does not support startup into a pre - biased condition. be sure the output capacitors are not charged or the output of the ep53 58xu i is not pre - biased when the ep53 58xui is first enabled. input filter capacitor for i load 500ma, c in = 2.2uf for i load > 500ma c in = 4.7uf. 0402 capacitor case size is acceptable. the input capacitor must use a x5r or x7r or equivalent dielectric formulation. y5v or equivalent diele ctric formulations lose capacitance with frequency, bias, and with temperature, and are not suitable for switch - mode dc - dc converter input filter applications. output filter capacitor for vin 4.3v, c out_min = 10uf 0603 mlcc. for vin > 4.3v, c out_min = 10uf 0805 mlcc. ripple performance can be improved by using 2x10 f 0603 mlcc capacitors (for any allowed vin) . the maximum output filter capacitance next to the output pins of the device is 60 f low esr mlcc capacitance. v out has to be sensed at the l ast output filter capacitor next to the ep5358 xui. additional bulk capacitance for decoupling and bypass can be placed at the load as long as there is sufficient separation between the v out sense point and the bulk capacitance. excess total capacitance on the output (output filter + bulk) can cause an over - current condition at startup. refer to the section on soft - start for the maximum total capacitance on the output. the output capacitor must use a x5r or x7r or equivalent dielectric formulation. y5v or equivalent dielectric formulations lose capacitance with frequency, bias, and temperature and are not suitable for switch - mode dc - dc converter output filter applications. www.altera.com/enpirion page 13 03541 october 11, 2013 rev f
ep5358lui/ep5358hui layout recommendation figure 10 shows critical components and layer 1 traces of a recommended minimum footprint ep5358lqi/ep5358hqi layout with enable tied to v in . alternate enable configurations, and other small signal pins need to be connected and routed according to specific customer application. please see the gerber files on the altera website www.altera.com/enpirion for exact dimensions and other layers. please refer to figure 10 while reading the layout recommendations in this section. recommendation 1: input and output filter capacitors should be placed on the same side of the pcb, and as close to the ep5358qi package as possible. they should be connected to the device with very short and wide traces. do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. the +v and gnd traces between the capacitors and the ep5358qi should be as close to each other as pos sible so that the gap between the two nodes is minimized, even under the capacitors. recommendation 2: input and output grounds are separated until they connect at the pgnd pins. the separation shown on figure 10 between the input and output gnd circuits h elps minimize noise coupling between the converter input and output switching loops. recommendation 3: the system ground plane should be the first layer immediately below the surface layer. this ground plane should be continuous and un - interrupted below th e converter and the input/output capacitors. please see the gerber files on the altera website www. altera.com/enpirion . figure 10 : top pcb layer critical components and copper for minimum footprint recommendation 4 : multiple small vias should be used to connect the ground traces under the device to the system ground plane on another layer for heat dissipation. the drill diameter of the vias should be 0.33mm , and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20 - 0.26mm . do not use thermal reliefs or spokes to connect the vias to the ground plane. it is preferred to put these vias under the capacitors along the edge of the gnd copper closest to the +v copper. please see figure 10. these vias connect the input/output filter capacitors to the gnd plane and help reduce parasitic inductances in the input and output current loops. if the vias cannot be placed under c in and c out , then put them just outside the capacitors along the gnd. do not use thermal reliefs or spokes to connect these vias to the ground plane. recommendation 5 : avin is the power supply for the internal small - signal control circuits. it should be connected to th e input voltage at a quiet point. in figure 10 this connection is made at the input capacitor close to the v in connection. www.altera.com/enpirion page 14 03541 october 11, 2013 rev f
ep5358lui/ep5358hui recommended pcb footprint figure 11 : ep5358 xui package pcb footprint www.altera.com/enpirion page 15 03541 october 11, 2013 rev f
ep5358lui/ep5358hui package and mechanical figure 1 2 : en53 5 8x u i package dimensions contact information altera corporation 101 innovation drive san jose, ca 95134 phone: 408 -544-7000 www.altera.com ? 2013 altera corporation ? confidential. all rights reserved. altera, arria, cyclone, enpi rion, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera corporation and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com/enpirion page 16 03541 october 11, 2013 rev f

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